library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.textio.all;

entity MUX2_tb is
end;

architecture bench of MUX2_tb is
   -- define the component
   component MUX2
      port( sel      : in   std_logic;
            A, B     : in   std_logic;
            output   : out  std_logic );
   end component;
   
   -- define the signals
   signal sel        : std_logic;
   signal A, B       : std_logic;
   signal output     : std_logic;
   
   -- define a constant time period
   constant PERIOD : time := 5 ns;
   
begin
   -- component instantiation
   DUT : MUX2 port map (   sel => sel,
                           A => A, B => B,
                           output => output );
                       
   test : process
   begin
      sel <= '0';
      A   <= '0';
      B   <= '0';
      wait for PERIOD;
      
      sel <= '0';
      A   <= '1';
      B   <= '0';
      wait for PERIOD;
      
      sel <= '0';
      A   <= '0';
      B   <= '1';
      wait for PERIOD;
      
      sel <= '0';
      A   <= '1';
      B   <= '1';
      wait for PERIOD;

      sel <= '1';
      A   <= '0';
      B   <= '0';
      wait for PERIOD;
      
      sel <= '1';
      A   <= '1';
      B   <= '0';
      wait for PERIOD;
      
      sel <= '1';
      A   <= '0';
      B   <= '1';
      wait for PERIOD;
      
      sel <= '1';
      A   <= '1';
      B   <= '1';
      wait for PERIOD;

      wait;
   end process test;
end bench;
